Design and Implementation of Sic MOSFET Three Phase Inverter Board

Designed and implemented the CMOS layout of a Spiking Neural Network (SNN) forward path in 22nm technology using Cadence Virtuoso. Developed software models for learning algorithm circuits in Python and Verilog-A on Cadence to simulate circuit behavior and verify functionality. Implemented a BPTT-based learning algorithm in SystemVerilog on Xilinx Vivado and integrated the model into Cadence using xmvlog, genus and innovus for verification. Automated complex training simulations using Ocean Scripts to optimize circuit performance. Achieved 95% accuracy with Post-Training Quantization and 80% accuracy with Quantization-Aware Training (on-chip training), demonstrating the feasibility of hardware-based SNN learning.

Design and analysis of different amplifiers and low dropout voltage regulator in 130nm technology in Cadence Virtuoso. Using state-space representation to model the non-linearity’s of these typologies. Implementation of a neural network model of analog circuits with nonlinearity using Tensorflow and Scikit-learn to implement the model on Xilinx FPGA for AMS emulation efficiently. Compared to stateof-the-art LUT methods, resource usage is reduced by 98.4%.

Electrical measurement of DePFET device with LabView and parameter extraction from measurements with Python. Implementation and Simulation of Charge-Based Model(EKV) of DePFET with VerilogAMS in Cadence Virtuoso.

Analyzed and optimized the assembly production line for automotive starters and generators. Conducted quality monitoring and statistical analysis of automotive generators and starters.