Work experience

• 失效分析工程师（美国）

  创客工场

  2025.07-Current

  (a month)
• Test Engineer

  Aivres

  2024.11-2025.07

  (9 months)

  Experienced Test Engineer specializing in data center server hardware testing and validation. Skilled in BIOS/BMC/CPLD/FPGA firmware testing with expertise in using MES systems for server diagnostics and defect tracking. Strong capability in Root Cause Analysis and semiconductor chip-level failure analysis. Proficient in mechanical inspection (VMI) of Server/GPU board components (motherboards, GPUs, CPUs, DIMMs, NICs, SSDs, and powersupplies) to ensure compliance with industry standards. Maintained 98% first-pass yield rate at Aivres Systems and Signal Electronic, reducing troubleshooting time from 3.5 hours to 45 minutes. Led development of firmware integrity validation protocols, preventing 15+ potential hardware security vulnerabilities. Experienced in data center infrastructure environmental testing including extreme condition simulation and component validation. Knowledgeable in semiconductor manufacturing processes and PCB assembly testing flows. Bilingual capabilities (English and Mandarin Chinese) allow seamless collaboration with international teams and clients. Seeking Test Engineer opportunities where I can leverage my skills in hardware testing, failure analysis, and quality assurance.
• Test Engineer

  Signal Electronic Maintenance LLC

  2023.03-2024.12

  (2 years)

  Architected and implemented end-to-end test methodologies for server systems, achieving 95% first-time validation rate and reducing test-related delays by 30% while maintaining comprehensive test coverage. Led BIOS/BMC/CPLD/FPGA firmware testing initiatives, creating automated test scripts that improved system reliability and reduced firmware-related failures by 20%. Led the diagnosis and resolution of a rare server motherboard power failure that only triggered under specific temperature and humidity conditions. Through designing specialized environmental simulation tests and precise circuit analysis, identified a design flaw in the power management chip, proposing a fix that was implemented across the entire product line. Documented detailed test procedures and results, creating a comprehensive knowledge base that decreased onboarding time for new engineers from 3 weeks to 5 days and improved team productivity by 35%. Participated in cross-functional design reviews, providing critical feedback that prevented 8 potential design flaws before production implementation and saved an estimated $500K in potential rework. Prioritized effective stakeholder communication, working closely with system administrators and development teams to resolve critical bugs, adjust testing approaches, and ensure seamless integration of server systems.

Educational experience

• Florida State University

  Master of Science in Information Technology

  2022.09-2023.12

  (a year)
• Rutgers University

  Bachelor of Science in Management Information Systems

  2019.09-2021.12

  (2 years)

Languages