Pranav Arya
Principal Application Engineer@Cadence Design Systems
Nationality
Share
Summary
Semiconductors, Advanced Nodes, Physical Design Engineer. Experienced Senior Application Engineer with expertise in Advanced Node (3nm, 5nm, 7nm) Mobile and HPC technologies with specialization in PPA and flow development. Skills: - Placement and Routing - Static Timing Analysis (with PT-ECO) - Design Floorplanning - DRC signoff - TCL/Perl programming Tools: - Fusion Compiler - IC Compiler-II - PrimeTime - IC Validator
Work experience
Principal Application Engineer
Cadence Design Systems2023.06-Current(3 years)Senior Application Engineer
Synopsys Inc2015.04-2023.05(8 years)Researcher
National Chiao Tung University2012.09-2015.02(2 years)Software Engineer - Associate Tech L2
Sapient Global Markets2011.01-2012.07(2 years)Software Developer (Assistant Systems Engineer)
TCS2008.10-2010.12(2 years)
Educational experience
National Chiao Tung University
Master of Science (MS), Electrical and Electronics Engineering2012.01-2014.01(2 years)Guru Gobind Singh Indraprastha University
B Tech, Electronics & Communication Engg.2004.01-2008.01(4 years)
Resume Search
Nationality
Job category
City or country
Sort by
Contact way
Membership will unlock the resume
Also view
