Senior Staff Engineer @ Qualcomm | Ex-TSMC | Ex-Synopsys | High Performance SRAM IP. As a Principal Design Engineer at TSMC, I lead the design and characterization of register files/memory circuits for high-performance and low-power applications. I have over six years of experience in SRAM circuit design, bitcell analysis, timing and power analysis, and read and write assist circuit design and analysis. I have a strong engineering background in VLSI design and CAD, with a master's degree from Thapar Institute of Engineering & Technology. I also have four years of experience as an R&D Engineer at Synopsys. I am proficient in Tcl scripting, and I speak English, and working level Chinese and some German. My goal is to contribute to the innovation and excellence of the semiconductor industry with my skills and expertise in SRAM.