Work experience

• Sr. Design & Verification Engineer / Team Lead

  Orion VLSI Technologies

  2024.02-Current

  (2 years)

  Developed complete UVM/SystemVerilog testbench for a secure RISC-V core from scratch, integrating SystemC ISS as golden reference model. Integrated PMP and cryptographic ASCON blocks; extended RTL with secure instructions. Drove functional and code coverage closure, regression stability and mentored junior engineers.
• dsp - verification engineer

  CEVA

  2019.02-2024.01

  (5 years)

  Applied Specman e and UVM methodology for DSP verification (Load/Store Unit, VPU, Winograd). Built instruction generators, memory models, scoreboards, and regression automation. Defined coverage plans, wrote assertions, executed regressions, and ensured coverage closure. Reported, analyzed, and tracked multiple RTL bugs to closure.

Educational experience

• Birzeit University.

  Electrical Engineering

  2012.09-2018.01

  (5 years)

  During my undergraduate studies at Birzeit University, I pursued a Bachelor of Science degree in Electrical Engineering. My academic journey was enriched by various technical projects, including participation as a team member in the projects "Steganography” and “PICMicro assembly Project.”

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