Control Engineer @ SCIVIC | MS ECE @ UCLA Digital IC & STA & CAD tools & Physical Design & PLC. As an intern at BTD Technologies, I developed rapid calculation methods for device and interconnect delay, and applied STA and Statistical static timing analysis (SSTA) algorithms in timing estimation and design for manufacturability under process variation. As a research assistant at Eastern Institute for Advanced Study, I conducted research on advanced technology nodes in VLSI, investigating multi-peak distributions in probability distributions and applying machine learning techniques to predict LVF library file generation. I also published a paper at the Design Automation Conference (DAC), showcasing my expertise in semiconductor design, research, and technical documentation. With expertise in programming languages such as C, C++, and Python, and proficiency in software tools including MATLAB, HSPICE, LTspice, Kicad, and ADS, I possess a strong foundation in programming and software development, enabling me to effectively design, simulate, and analyze complex systems and circuits.