We are seeking a motivated and experienced IO Design Engineer to join our advanced Memory Design team. The ideal candidate will have 5 to 8 years of direct experience in designing and analyzing high-speed IO interfaces for memory products. In this role, you will be instrumental in the architecture, design, and validation of high-performance interfaces for our next-generation DRAM and HBM products. Key Responsibilities: Design, develop, and characterize high-speed IO circuits (e.g., DDR, LPDDR, HBM) for advanced DRAM products. Perform transistor-level circuit design, simulation, and optimization for critical interface blocks such as drivers, receivers, impedance calibration (ZQ), and on-die termination (ODT). Collaborate closely with layout engineers to implement optimal floorplans and physical designs, ensuring performance and robustness. Work with product and test engineers to define test plans, support silicon bring-up, debug, and characterization, and perform failure analysis.

Master’s degree in Electrical Engineering or a related field, or a Bachelor's degree with equivalent experience. 5 to 8 years of professional experience in semiconductor circuit design. Proven hands-on experience in the design and analysis of high-speed IO interfaces. Direct design experience with at least one of the following: DRAM (DDR3, DDR4, DDR5, LPDDR4/5) or High-Bandwidth Memory (HBM/HBM2e). Strong understanding of CMOS design fundamentals and analog/mixed-signal concepts. Proficiency with circuit simulation tools (HSPICE, FineSim, Spectre) and waveform debugging.