Yi Xian Lim

SoC Physical Design Engineer@MediaTek
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Summary

SoC Timing Closure Engineer. Developing myself in the semiconductor industry and a graduate from Universiti Teknologi Malaysia, who is responsible and time conscious in completing tasks. Enjoy working in a team and meeting new friends. Also, curious about new things which prompted me to learn new knowledge all the time. Looking forward to implement, as well as expand my skills and knowledge in the industry. Fluent in Chinese, English and Malay.

Work experience

  • SoC Physical Design Engineer

    MediaTek
    2021.11-Current(5 years)
  • Intern

    Intel Corporation
    2020.07-2020.10(4 months)

Educational experience

  • Georgia Institute of Technology

    Master of Science - MS, Computer Science
    2024.01-2027.01(3 years)
  • Universiti Teknologi Malaysia

    Bachelor of Engineering - BE, Electronics Engineering
    2017.01-2021.01(4 years)
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