Work experience

• Senior Staff Engineer- Firmware

  Samsung Semiconductor India Research

  2022.11-2025.10

  (3 years)

  Roles and Responsibilities: FW Design, Development and Testing of RISC V CPU based CMOS Image Sensor SoCs for Smartphones Design and develop code for various modules of Timing generator, Power Spreader, Power domains, DCG and HDR blocks block in ISP pipeline Pre-silicon and post silicon bring up of the Image sensor SoC Run and verify RTL simulations for Timing Generator, Power spreader blocks functionality in Image sensor for multiple functional modes Work with RTL team to bring up the Timing generator, Power spreader blocks if any issue found in RTL simulations Prepare setfiles of various functional modes like FULL, FDsum, A2A2, AON for customer release and internal evaluation Configuration of different Power domains in Always ON and Deep Sleep modes. Update Image size, IP enable/disable settings as per sensor FPS sheet in the setfiles for various modes Verify the prepared setfiles on RTL simulations, FPGA before tapeout and on Package after post silicon Discuss and work with RTL and Analog design, verification teams for FW features, functionality and usage of the IP and overall system impact. Resolve customer queries regarding features enablement and usage Work with solutions team to verify all IP/System FW functionalities Debug the customer/solution team reported issues and resolve them Test plan preparation, Test case development and execution of DCG, power spreader, Analog gain using RTL simulations and python scripts on FPGA and silicon
• Software Engineer

  NXP Semiconductors

  2018.12-2022.08

  (4 years)

  Roles and Responsibilities: FW Development and Testing activities for DSP and ARM cortex-M33 processors for UWB(Ultra Wide Band) RF SoC FW development and Unit testing for Bootloader of ROM, Radar, RF, SPI drivers, Crypto, Firewall Code coverage on FPGA and silicon using Ulink Pro ETM. Test plan preparation and execution for different FW features(Host Interface, RF Comm.,Calibration) using python scripts on simulation and silicon
• Senior Engineer (Level-1)

  E-Infochips Limited

  2015.08-2017.04

  (2 years)

  Roles and Responsibilities: Participate in Architecture design and usage scenario discussions Generation of Test Plan based on SOC Design Document to verify SOC functionalities (controller, IPs,System) for a leading chip design company. Development of Firmware as per functional test and coverage plan and Run Firmware on ASIC RTL Debug Firmware on RTL using ASIC simulation tools and Report the designer, if any design bug is there. Working with the design and verification teams to close the bugs before RTL freeze and chip tapeout. Design, develop and debug SOC platform software for Avionics domain. Involve in daily scrum, sprint planning, sprint retrospective, sprint demo meetings.
• Senior Embedded Engineer

  Reve Automation LLP

  2012.04-2015.08

  (3 years)

  from April 2012 to August 2015 Roles and Responsibilities: Project requirement analysis and select development tools, microcontroller, parts based on it Design, develop and debug Firmware for various analog and digital sensors interfacing, RF sensor networks, security systems and robotics Design, develop and debug software for Image processing applications Design Hardware schematic and PCB for sensors and control panels Bring up and troubleshooting PCB and system hardware and firmware Lead team members in various life cycles of project Client interaction for requirement understanding and support Projects:
• Embedded Engineer

  IMP Consultancy

  2010.12-2012.03

  (a year)

  Roles and Responsibilities: Firmware development and testing of 8-bit microcontrollers for data loggers and door interlocking system using Embedded C Hardware development and testing for data loggers and door interlocking system with Proteus.
• Project Engineer

  Maharshi Electronic Systems

  2008.11-2009.07

  (9 months)

  Roles and Responsibilities: Development and testing of Image processing software modules for IMDPS at Space Application centre-ISRO, Ahmedabad using C language on Linux platform Testing of MIND (Manipulation of Images and Data) software, having features such as multiplication of two images, adding salt and pepper noise, band pass filter, low pass filter, high pass filter, wiener filter, radius v/s power plot etc.
• Project Trainee

  GlobalTech (India) Pvt. Ltd.

  2008.01-2008.04

  (4 months)

  Project: Universal Transceiver Macrocell Interface (USB 2.0 protocol) Description: ● The Primary focus of UTMI is to shift the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic in the ASIC. ● It eliminates high speed USB 2.0 logic design for peripheral developers. It supports HS/FS, FS only and LS only UTM implementations.

Educational experience

• Hemchandracharya North Gujarat University

  Electronics and Communication Engineering

  2004.07-2008.05

  (4 years)

  Electronics and Communication Engineering with Focus on VLSI design and Embedded Systems

Languages

Skills