Zhenyu Xu
Senior Member of Technical Staff@AMD
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Summary
SMTS at AMD. I am a Master student in Stony Brook University. I am a research assistant in CEWIT (Automatic Hardware Generation & Optimization Lab) under Prof. Peter Milder of designing a digital system in kmer counting in Xilinx Zedboard. I have two publications on FPGA in my undergraduate study. I am proficient in digital circuit design, system generation and testing, computer architecture. I am proficient in Verilog/SystemVerilog, C/C++ and I know Java and Python. I also have deep understanding in mixed-siganl circuit and semiconductor manufacture. I am now seeking full-time job in digital circuit/FPGA design or verification.
Work experience
Senior Member of Technical Staff
AMD2023.07-Current(3 years)MTS Silicon design Engineer
AMD2021.07-2023.07(2 years)Sr ASIC/Layout Design Engineer
AMD2018.07-2021.06(3 years)ASIC/Layout Design Engineer 2
AMD2016.01-2018.06(2 years)Research Assistant
Stony Brook University2015.01-2015.12(a year)Research Assistant
Tianjin University2013.03-2014.05(a year)Summer Internship
LEAD Electrical Corporation2013.07-2013.08(2 months)
Educational experience
Stony Brook University
Master's Degree, electrical and computer engineering, 3.912014.01-2015.01(a year)Tianjin University
Bachelor's Degree, Integrated Circuit Design, 852010.01-2014.01(4 years)
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