Work experience

• Senior Design Engineer

  Microchip Technology

  2023.01-Current

  (3 years)

  MicrochipTechnology Lead SoC Design signoff and FPGA timing closure for PolarFire and PolarFireSoC2platforms. Performed SoC Design, Lint, Synthesis and full-chip timing signoff usingCadence Genus and Tempus. Developed and optimized integrations for AXI4-Lite compliant NoC, SSN, IJTAG, and mBIST network. Supported design of AXI4-Lite based NoC microarchitectures and constraints. Supported design constraints of multiple CSCB-related blocks. Managed design and DFT bus signoffs across multiple variants.
• Design Engineer

  Micron Technology

  2019.09-2023.01

  (3 years)

  Supported RTL Design for multiple DDR blocks. Used Synopsys PrimeTime for STA with TCL and Python scripting. Worked on RTL Design and timing signoffs for DDR5, LPDDR5, and HBM3 memory blocks. Focused on mBIST, P1500, ECC, and Command Decoder. Supported design constraints for multiple Self Refresh and RHR blocks. Verified multiple DDR4, DDR5, LPDDR4/5 memory projects using gate-level simulation. Led verification for Self-Refresh, RHR, and CAM blocks. Improved verification methodologies and collaborated across global teams. Contributed to JEDEC-compliant DDR5 spec reviews and coverage analysis.

Educational experience

• RTM University, Nagpur

  VLSI Design

  2015.07-2017.07

  (2 years)

  Completed M.Tech in VLSI Design with First class

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